Integrated circuit memories continue to increase in storage capacity, use, and complexity. With each of these factors, there is an ongoing need to design and manufacture such memories as efficiently as possible, thereby minimizing cost and layout size while maximizing reliability and speed. The present invention balances each of these goals in the context of an integrated circuit having an odd number of input/output ("I/O") contact pads for coupling to a memory. Further, the invention is particularly beneficial where the odd number of I/O contact pads are spread over a relatively large linear region and have a relatively large distance between successive contact pads.
FIG. 1 diagrammatically illustrates an integrated circuit 10 which includes a memory array 12. Memory array 12 includes a plurality of internal data storage locations (not shown). Integrated circuit 10 also includes a plurality of data contact pads C.sub.1 through C.sub.9 and a plurality of address contact pads A.sub.1 through A.sub.N. Both types of contact pads (i.e., data or address) are often referred to in the art as bond pads because, once integrated circuit 10 is included in an integrated circuit package, the package includes electrical pins which are electrically connected to respective bond pads via "bond wires". For purposes of the present discussion, however, it is not critical how such connections are made, but rather, only to note that the contact pads provide a contact for electrically communicating either a data or address value.
Memory array 12 includes data contacts MD.sub.1 through MD.sub.9 which are connected via a data bus 14 to contact pads C.sub.1 through C.sub.9. Integrated circuit 10 further includes an address decode circuit 16 connected between contact pads A.sub.1 through A.sub.N and memory array 12. In operation, data contact pads C.sub.1 through C.sub.9 may be electrically contacted for communicating data for outputting, inputting, or both outputting and inputting, between each pad and the storage cells of memory array 12 via data bus 14. For purposes of FIG. 1, it is assumed that each pad C.sub.1 through C.sub.9 can serve both an input and output operation and, therefore, these pads are considered I/O pads as known in the art. Moreover, as also well established in the art, an address is connected to address pads A.sub.1 through A.sub.N, and decoded by circuit 16 to address a particular row within memory array 12. In response, the data values along that row are either output from the row and columns to data contact pads C.sub.1 through C.sub.9, or written to those locations from data contact pads C.sub.1 through C.sub.9.
The linear span of data contact pads C.sub.1 through C.sub.9 relative to the size and placement of memory array 12 affects design efficiency. For purposes of demonstrating this as well as various objects of the present invention, contact pads C.sub.1 through C.sub.9 in FIG. 1 span a linear length on the order of 0.400 inch, and each successive pad is approximately 0.040 inch apart from its nearest neighboring pad. The location of the pads raises design issues about the layout of location memory array 12, and the connection and layout of data bus 14. For example, if memory array 12 is small in dimension relative to the linear distance between data contact pads C.sub.1 through C.sub.9, then the delay time from one array data contact to its corresponding data contact pad may significantly differ between a differing array data contact and its corresponding data contact pad. For example, FIG. 1 is emphasized in this regard to show that the distance between MD.sub.1 and C.sub.1 is longer than the distance between MD.sub.5 and C.sub.5. Thus, the communication delay between the second group of contacts will be shorter. In addition, greater bus lengths introduce greater capacitance, and otherwise reduce design efficiency and device operability. Still further, if memory array 12 is not symmetrically located with respect to pads C.sub.1 through C.sub.9, construction of the circuit is more complicated due to such asymmetries. Lastly, although not shown in FIG. 1, a memory such as that shown may include multiple columns corresponding to each data contact MD.sub.1 through MD.sub.9. Moreover, for a given data access, and although not shown, one of the multiple columns from MD.sub.1 may provide data for connecting to contact C.sub.9. Thus, still additional data busing is necessary, thereby increasing busing length and complexity creating problems such as those identified above.
It is therefore an object of the present invention to provide an integrated circuit with widely spread contact pads and particularly designed memory arrays for an efficient layout in view of the contact pad layout.
It is a further object of the present invention to provide such an integrated circuit with unequally-sized paired memory arrays which are selectively coupled to the data contact pads of the integrated circuit.
It is a further object of the present invention to provide such an integrated circuit with unequally-sized paired memory arrays which are selectively coupled to an odd number of data contact pads on the integrated circuit.
It is a further object of the present invention to provide such an integrated circuit with sets of paired memory arrays situated in a fashion symmetric with respect to other paired memory arrays of the circuit.
It is a further object of the present invention to provide such an integrated circuit with sets of paired memory arrays situated in a fashion symmetric with respect to the data contact pads of the integrated circuit.
It is a further object of the present invention to provide such an integrated circuit with sets of paired memory arrays situated in a fashion so as to minimize wasted area on the integrated circuit.
Still other objects and advantages of the present invention will become apparent to those of ordinary skill in the art having references to the following specification together with its drawings.